1. Field of the Invention
The present invention relates to a semiconductor memory device arranged in which each memory cell comprises a variable resistance element having two-port structure for storing information by varying its electrical resistance between a first state and a second state when receiving different polarity voltages at the two ports respectively and a cell access transistor connected at the drain to one port of the variable resistance element and more particularly to an action of writing the memory state of the memory cell.
2. Description of the Related Art
Recently, there have been increased a number of occasions for using cash cards, credit cards, prepaid cards in common livings. Conventionally, most of such cards are implemented by magnetic cards for storing information. As personal information has to be handled with much care, the magnetic cards are now being replaced by IC cards which are much easier to take security measures.
Such IC cards preferably employ nonvolatile semiconductor memory devices where the information is saved and not deleted when being disconnected from power sources. Nonvolatile semiconductor memory devices include typically flash memories and FeRAMs. Those types however have trade-off relationship between the high speed operation during the writing action, the power consumption, and the durability to the writing action. Accordingly, various studies have been attempted for satisfying two or more of the requirements in the nonvolatile semiconductor memory devices. One of the mostly feasible studies proposes a variable resistance type of nonvolatile semiconductor memory device where a variable resistance type nonvolatile memory cell is provided for varying its electrical resistance when receiving an electric stress such as application of voltage and holding its resistance state at a nonvolatile mode. This type of nonvolatile semiconductor memory device is highly prospective as improved in the high speed operation, the low power consumption, and the mass storage size.
The variable resistance element in such a variable resistance type nonvolatile semiconductor memory device may commonly be a made by a manganese-containing oxide material having a perovskite crystalline structure, such as Pr1−xCaxMnO3 (where 0<x<1, referred to as PCMO hereinafter) which has properties of colossal magnetoresistance (CMR) and high temperature superconductivity (HTSC) (See “Novel colossal magnetoresistive thin film nonvolatile resistance random access memory (RRAM)” by Zhuang H. H. et al, IEDM Report No. 7.5, December 2002). The manganese-containing oxide material is varied in the resistance value when receiving pulses of voltage. As its resistance value is related to information, the material can be used as a memory element in the semiconductor memory device.
FIG. 14 illustrates a profile of the switching characteristic of the electrical resistance of PCMO disclosed in the above described citation. The switching characteristic graphically shown in FIG. 14 is a change of the resistance value in the case when the pulses of ±5 V for 100 ns are applied to the PCMO having a thickness of 100 nm alternatively, where the vertical axis indicates a resistance value and the horizontal axis indicates the number of pulse application. When receiving the pluses of voltage which are different in the polarity, the PCMO is varied in the resistance value ranging from 1 kΩ to 1 MΩ. Since its resistance value is varied within a range as wide as three digits, the PCMO can favorably be used as a variable resistance element in the nonvolatile semiconductor memory device.
More particularly for being practically utilized in the form of a memory cell in the variable resistance type nonvolatile semiconductor memory device, the above described variable resistance element is accompanied with a cell access transistor to form a 1T1R (one transistor and one resistance element) construction (as disclosed in, for example, Japanese Unexamined Patent Publications No. 2005-25914, No. 2004-185755, and No. 2004-158119). One memory cell of the 1T1R construction is shown in FIG. 15 where the variable resistance element having two-port structure is connected at one port to either the drain or the source of a cell access transistor to form a series circuit. The cell access transistor may preferably be an n-channel MOSFET in consideration with the layout area size or the like.
FIG. 16 illustrates an example of an array of the 1T1R type memory cells shown in FIG. 15 and arranged in rows (along the vertical direction in FIG. 16) and columns (along the horizontal direction in FIG. 16). The cell access transistors in the memory cells aligned along one row are connected at the gate to a common word line extending along the row. Similarly, the cell access transistors in the memory cells aligned along one column are connected at the drain to a common bit line extending along the column. The other port of the variable resistance element in each memory cell is connected to a source line which extends along the row or column (as denoted by the grounding mark for each memory cell in FIG. 16). The source lines may be provided along their respective rows or columns or connected as common lines to the memory cell arrays or in any other applicable fashion. In general, the source lines are connected via the n-channel MOSFETs to the ground as disclosed in Japanese Unexamined Patent Publication No. 2004-158119.
Using the 1T1R type of the memory cell or memory cell array in the variable resistance type nonvolatile semiconductor memory device, as shown in FIGS. 15 and 16, the variable resistance element in the memory cell has to be supplied with a positive voltage from the bit line via the cell access transistor in the memory cell when a program or erase voltage is applied between the two ports of the variable resistance element in order to increase or decrease its electrical resistance. When the cell access transistor is supplied with the positive voltage at both the drain and the gate, a voltage drop equal to the amplitude of the threshold voltage assigned to the cell access transistor will occur at the source of the cell access transistor. It is hence necessary for supplying between the two ports of the variable resistance element with the voltage at a sufficient amplitude to boost the positive voltage before being applied to the drain or gate of the cell access transistor by an increase which can offset the drop in the voltage equal to the threshold voltage. This requires a boosting circuit to be added, thus increasing the tip size and thus the production cost of the semiconductor memory device.
Also, since the variable resistance elements in the memory cells in the memory cell array shown in FIG. 16 are directly connected with the source lines, they may be supplied with the positive voltage directly from the source lines. However in most cases, the voltage of the source lines is set with the n-channel MOSFETs of which the threshold voltage in turn causes a voltage drop. Accordingly, when the variable resistance element is supplied with the voltage at both, positive and negative, polarities between its two ports for conducting the erasing or programming action, a voltage drop equal to the threshold voltage will be inevitable.